1. Field of the Invention
The present invention relates to a method for acquiring a plurality of semiconductor devices from a semiconductor wafer, that is, for manufacturing a semiconductor device.
2. Description of Related Art
To meet the needs of downsized electronic device featuring increased functionally, a semiconductor device called a chip on chip (CoC) in which a plurality of semiconductor chips are laminated on each other has been developed in recent years. Japanese Patent Application Laid-Open No. 2010-251347(hereinafter referred to as patent document 1) discloses a method for manufacturing a CoC type semiconductor device. The method includes the steps of: laminating a plurality of semiconductor chips on each other; filling an underfill in the clearances between the semiconductor chips disposed next to each other to thereby form a chip laminated body; and mounting the chip laminated body on a wiring board. The semiconductor chip is formed by dividing a semiconductor wafer having a circuit and the like formed thereon into individual chip regions.
Japanese Patent Application Laid-Open No. 8-321478 (hereinafter referred to as patent document 2) discloses a method for manufacturing a semiconductor device. The method includes a step of cutting a bonded body, which is made by bonding a semiconductor substrate having a plurality of semiconductor device patterns formed thereon repeatedly to an insulating substrate, along cutting regions to thereby separate the bonded body into individual semiconductor devices. In this method, before the semiconductor substrate is bonded to the insulating substrate, first cuttings (half cuttings) are formed in regions corresponding to the cutting regions of the insulating substrate. Then, after the semiconductor substrate is bonded to the insulating substrate, the bonded body is separated into individual semiconductor devices by second cuttings (full-cuttings).
Japanese Patent Application Laid-Open No. 2007-157974 (hereinafter referred to as patent document 3) discloses a method for manufacturing a resin sealing material in which a single body of a semiconductor chip is sealed. In this method, first, a plurality of semiconductor chips are arranged at intervals in the shape of a lattice and then the plurality of semiconductor chips are sealed by resin, whereby a resin sealing material is formed in which the plurality of semiconductor chips are sealed. Half cuttings are formed on one face of the resin sealing material in a longitudinal direction and in a lateral direction in such a way that the semiconductor chips are individually divided. Thereafter, the resin sealing material is fully cut by a dicing blade from a face (bottom face) having an external electrode formed thereon along the groove-shaped lines of the half-cuttings. In this way, the resin sealing material in which the single bodies of the semiconductor chips are sealed is individually divided into the single bodies of the semiconductor chips.
In the CoC type semiconductor device described in the patent document 1, the semiconductor chip that makes up the chip laminated body has bump electrodes formed on both faces thereof. These bump electrodes are connected to other semiconductor chip and/or a wiring board. The semiconductor chip is manufactured by cutting and separating a semiconductor wafer including a plurality of semiconductor chips into individual chip regions. When the semiconductor wafer is cut, usually, one face of the semiconductor wafer is made to adhere to and to be held by a dicing tape.
The semiconductor wafer including the plurality of semiconductor chips having the bump electrodes formed on both faces thereof needs to be placed onto the dicing tape in such a way that the bump electrodes are embedded in the adhesive material layer of the dicing tape. For this reason, the adhesive material layer needs to be made comparatively thick.
However, in the case where the thickness of the adhesive material layer of the dicing tape is made thick, cutting the semiconductor wafer with a dicing blade that rotates at a high speed, easily causes chipping (cracking) to occur in the bottom face of the semiconductor wafer (semiconductor chip). This is because the side faces of the dicing blade rotating at the high speed come into contact with an edge of the bottom face (face on which the dicing tape is placed) of the cut semiconductor chip. When the edge of the semiconductor chip is chipped off, the strength and reliability of the semiconductor chip are likely to be reduced. Further, in the case where the bump electrodes are arranged near the periphery of the semiconductor chip, the bump electrodes can be also damaged in some cases by the chipping of the semiconductor chip.
The patent document 2 and the patent document 3 do not disclose the problem in which chipping is caused by the bottom face of the semiconductor chip interfering with the dicing blade at the time of dicing because of the dicing tape having the thin adhesive material layer in which the bump electrodes need to be embedded.